International Journal Papers

[Accepted] Soyeon Choi, Yunjin Noh, Heehun Yang, Eunsang Kwon, Giyoung Kim, and Hoyoung Yoo, “HW/SW Co-design Method for Data Acquisition System on Xilinx RFSoC”, IEIE Transactions on Smart Processing and Computing Journal, Nov. 2024.
Nari Im, Heehun Yang, Yujin Eom, Seong-Cheon Park and Hoyoung Yoo, “Efficient Twiddle Factor Generators for NTT”, Electronics, vol. 13, no.16, pp.1-12, Aug. 2024.
Jihwan Lim, Jeonghun Son and Hoyoung Yoo, “Efficient Processing-in-Memory System Based on RISC-V”, Electronics, vol. 13, no.15, pp.1-11, Jul. 2024.
Soyeon Choi, Heehun Yang, Yunjin Noh, Giyoung Kim, Eunsang Kwon and Hoyoung Yoo, “FPGA-Based Multi-Channel Real-Time Data Acquisition System”, Electronics, vol. 13, no.15, pp.1-13, Jul. 2024.
Heehun Yang, Jiho Park, Jooseung Lee, Hui-Myoung Oh, Soonwoo Lee, and Hoyoung Yoo, “TRNG-PUF Integration Utilizing Programmable Delay Logics on FPGAs”, Journal of Semiconductor Technology and Science, vol. 24, no.03, pp.240-248, Jun. 2024.
Muhammad Junaid, Hayotjon Aliev, SangBo Park, HyungWon Kim, Hoyoung Yoo, Sanghoon Sim, “Hybrid Precision Floating-Point (HPFP) Selection to Optimize Hardware-Constrained Accelerator for CNN Training,” Seonsors, vol. 24, no. 7, pp. 1-22, Mar. 2024.
Soyeon Choi, and Hoyoung Yoo, “Approaches to Extend FPGA Reverse-Engineering Technology from ISE to Vivado,” Electronics, vol. 13, no. 6, pp. 1-16, Mar. 2024.

Soyeon Choi, Yerin Shin, Kiho Lim, Hoyoung Yoo, “Efficient Partially-Parallel NTT Processor for Lattice-based Post-Quantum Cryptography”, Journal of Semiconductor Technology and Science, vol. 22 no. 6, pp. 459-474, Dec., 2022.
Nari Im, Soyeon Choi, and Hoyoung Yoo, “S-box Attack using FPGA Reverse Engineering for Lightweight Cryptography,” IEEE Internet of Things Journal, vol. 9, no. 24, pp. 25165-25180, Dec. 2022.

Byeong Yong Kong, Youngjoo Lee, and Hoyoung Yoo, “On the Hardware Complexity of Tree Expansion in MIMO Detection,” Journal of Semiconductor Engineering, vol. 2, no. 3, pp. 136–141, Dec. 2021.
Jiwoon Park, Minsu Kim, Gwanghee Jo, and Hoyoung Yoo, “Area-Efficient Universal Code Generator for GPS L1C and BDS B1C Signals”, Electronics, vol.10, no.22, pp. 1-14, Nov. 2021
Minsu Kim, Jiwoon Park, Gwanghee Jo, and Hoyoung Yoo, “Area-Efficient Universal Code Generator for Multi-GNSS Receivers”, Electronics, vol.10, no.20, pp. 1-14, Oct. 2021
Dongyun Kam, Hoyoung Yoo, and Youngjoo Lee, “Ultra-Low-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism”,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.29, no.6, pp. 1083-1094, June, 2021

Soyeon Choi, Youngjoo Lee, and Hoyoung Yoo, “Recent Successive Cancellation Decoding Methods for Polar Codes”,Journal of Semiconductor Engineering, vol.1, no.2, pp.74-80, Sept, 2020
Soyeon Choi and Hoyoung Yoo, “Fast Logic Function Extraction of LUT from Bitstream in Xilinx FPGA”,Electronics, vol.9, no.7, pp. 1-11, July, 2020
Jiwoon Park and Hoyoung Yoo, “Area-Efficient Differential Fault-Tolerant Encoding for Finite State Machines”, Electronics, vol.9, no.7, pp. 1-13, July, 2020
Soyeon Choi, Jiwoon Park, and Hoyoung Yoo,“Reverse Engineering for Xilinx FPGA Chips using ISE Design Tools,” Journal of Integrated Circuits and Systems , vol.6, no.1, January. 2020.
Hwasoo Shin, Soyeon Choi, Jiwoon Park, Byeong Young Kong, and Hoyoung Yoo,“Area-Eﬃcient Error Detection Structure for Linear Feedback Shift Registers,” Electronics , vol.9, no.1, January. 2020.

Hyeonkyu Kim and Hoyoung Yoo, “Area-Efficient Two-Dimensional Separable Convolution Structure,” IS&T Journal of Imaging Science & Technology , vol.63, no. 5, Sep. 2019.
Soyeon Choi and Hoyoung Yoo, “Area-efficient early termination technique for belief-propagation polar decoders,” Electronics , vol.8, no.9, pp.1-11, Sep. 2019.
Jihyuck Jo, Han-Gyu Kim, In-Cheol Park, Bang Chul Jung, and Hoyoung Yoo, “Modified Viterbi Scoring for HMM-based Speech Recognition,” TSI Press Intelligent Automation & Soft Computing, vol.25, no.8, pp. 351-358, June. 2019.
Soyeon Choi and Hoyoung Yoo, “Area-Efficient Early Termination for Belief Propagation Decoders of Polar codes,” IEIE Transactions on Smart Processing and Computing , vol.8, no.3, pp. 236-243, June. 2019.

Youngjoo Lee, In-Cheol Park, and Hoyoung Yoo, “Area-Optimized Syndrome Calculation for ReedSolomon Decoder,” IEIE Journal of Semiconductor Technology and Science, vol. 18, no.5, pp. 609-615, Oct. 2018.
Hoyoung Yoo and Youngjoo Lee, “Energy-efficient key-equation solving algorithm for BCH decoding,” IEIE Journal of Semiconductor Technology and Science, vol. 18, no. 4, pp. 518-524, Aug. 2018.
Eunmi Chu, Hoyoung Yoo, and Bang Chul Jung, “Resource usage of LTE networks for M2M group communications: modeling and analysis,” Elsevier Computers and Electrical Engineering, vol. 71, pp. 321-330, Oct. 2018.

Hoyoung Yoo and In-Cheol Park, “Efficient Pruning for Successive-Cancellation Decoding of Polar Codes,” IEEE Communications Letters, vol. 20, no. 12, pp. 2362-2365, Dec. 2016.
Byeong Yong Kong, Hoyoung Yoo, and In-Cheol Park, “Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 63, no. 7, pp. 673-677, Jul. 2016.
Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, “Low-Power Parallel Chien Search Architecture Using a Two-Step Approach,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 63, no. 3, pp. 269-273, Mar. 2016.
Jihyuck Jo, Hoyoung Yoo, and In-Cheol Park, “Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 2, pp. 754-758, Feb. 2016.

Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, “Efficient Parallel Architecture for Linear Feedback Shift Registers,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 62, no. 11, pp. 1068-1072, Nov. 2015.
Hoyoung Yoo and In-Cheol Park, “Partially Parallel Encoder Architecture for Long Polar Codes,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 62, no. 3, pp. 306-310, Mar. 2015.

Youngjoo Lee, Hoyoung Yoo, Injae Yoo, and In-Cheol Park, “High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-state Drives,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, pp. 1183-1187, May 2014.

Hoyoung yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park, “Area-Efficient Multimode Encoding Architecture for Long BCH Codes,” IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 60, no. 12, pp. 872-876, Dec. 2013.
Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park, “A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory,” IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2531-2540, Oct. 2013.

Youngjoo Lee, Hoyoung yoo, and In-Cheol Park., “Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, no. 8, pp. 522-526, Aug. 2011.
H. Yoo, Y. Lee, and I.-C. Park., “Area-Efficient Syndrome Calculation for Strong BCH Decoding,” Electronics Letters, vol. 7, no. 2, pp. 107-108, Jan. 2011.