[IDEC] Verilog HDL

• To be uploaded as follows.
• 1일차 오전
  • Verilog HDL Introduction
  • Lexical Basics

• 1일차 오후
  • Module & Port
  • Gate Level Modeling
  • Modelsim progrma

• 2일차 오전
  • Dataflow Level Modeling

• 2일차 오후
  • Behavioral Level Modeling
  • Useful Technique
  • QuartusII program